An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder

In this paper, an ultra low power front-end circuit for an UHF RFID tag is presented. In order to minimize the power consumption, a novel data decoder is proposed, which removes the need for high frequency oscillator. In addition, a dual voltage multiplier scheme is employed, which increases the power efficiency. Simulation results shows that the proposed circuit reduces the power consumption by an order magnitude compared to conventional RFID front-end circuits that use high frequency oscillators and single voltage multiplier.