Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability)...
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| creator | Perez H, W.J. Medina, J.V. Ravotto, D. Sanchez, E. Reorda, M.S. |
| description | Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability); however, the method requires effective techniques for generating suitable test programs. In this paper we face the issue of generating programs to test data caches (in particular their control part): a method is proposed, and some experimental results are provided to assess its effectiveness. |
| doi_str_mv | 10.1109/DDECS.2008.4538813 |
| format | Conference Proceeding |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic testing Built-in self-test Cache memories Cache memory Circuit testing Costs Integrated circuit testing Manufacturing processes Microprocessor testing Microprocessors Software testing System testing System-on-Chip testing |
| title | Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs |
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