Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability)...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Perez H, W.J., Medina, J.V., Ravotto, D., Sanchez, E., Reorda, M.S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic testing Built-in self-test Cache memories Cache memory Circuit testing Costs Integrated circuit testing Manufacturing processes Microprocessor testing Microprocessors Software testing System testing System-on-Chip testing
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability); however, the method requires effective techniques for generating suitable test programs. In this paper we face the issue of generating programs to test data caches (in particular their control part): a method is proposed, and some experimental results are provided to assess its effectiveness.
DOI:	10.1109/DDECS.2008.4538813