1T2R Structure with Cross-Spacer for High-Density Phase Change Memory

A novel 2-bit per cell architecture is proposed for high density phase change memory (PCM) array. One transistor controls one pair of cross-spacer type memory cells through a common bottom electrode. Such configuration so-called "chain structure" shows advantages in either enhanced memory density or enhanced current driving capability. In this paper, a 1 k bits test array is demonstrated, in which a minimum reset current about 0.4 mA is provided by a 3.3 V NMOS transistor (0.18 um CMOS technology).