A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications
A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm 2 . The cell size of 0.024μm 2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively s...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 82 |
|---|---|
| container_issue | |
| container_start_page | 81 |
| container_title | |
| container_volume | |
| creator | Fastow, R. Banerjee, R. Bjeletich, P. Brand, A. Chao, H. Gorman, J. Guo, X. Heng, J.B. Koenigsfeld, N. Ma, S. Masad, A. Soss, S. Woo, B.J. |
| description | A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm 2 . The cell size of 0.024μm 2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and excellent cycling behavior. |
| doi_str_mv | 10.1109/VTSA.2008.4530808 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4530808</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4530808</ieee_id><sourcerecordid>4530808</sourcerecordid><originalsourceid>FETCH-ieee_primary_45308083</originalsourceid><addsrcrecordid>eNp9z09OhDAUgPH6L5HROYBx8y4AvpYCZUmIEzfOJEKMu0nDlKH6KISiZjybZ_BMbsatq2_xW32M3XCMOMf87rmuikggqkgmMSpUJ2yZZ4pLISVPeaJOWSDSHEPFM3nGFn8g8ZwFPBEyzNL05ZItvH9FFJjEWcDeCpCJ62G9eYIVad9BbZrODTTsD_Bp5w4qQ21YkN07s4NycLNuZg_a7QAjFPLnuxdQGiKo7JeBdpjg8Z1mG5L5MATFOJJt9GwH56_ZRavJm-WxV-x2dV-XD6E1xmzHyfZ6OmyPc_H_-guTv0x8</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Fastow, R. ; Banerjee, R. ; Bjeletich, P. ; Brand, A. ; Chao, H. ; Gorman, J. ; Guo, X. ; Heng, J.B. ; Koenigsfeld, N. ; Ma, S. ; Masad, A. ; Soss, S. ; Woo, B.J.</creator><creatorcontrib>Fastow, R. ; Banerjee, R. ; Bjeletich, P. ; Brand, A. ; Chao, H. ; Gorman, J. ; Guo, X. ; Heng, J.B. ; Koenigsfeld, N. ; Ma, S. ; Masad, A. ; Soss, S. ; Woo, B.J.</creatorcontrib><description>A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm 2 . The cell size of 0.024μm 2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and excellent cycling behavior.</description><identifier>ISSN: 1524-766X</identifier><identifier>ISBN: 1424416140</identifier><identifier>ISBN: 9781424416141</identifier><identifier>EISSN: 2690-8174</identifier><identifier>EISBN: 9781424416158</identifier><identifier>EISBN: 1424416159</identifier><identifier>DOI: 10.1109/VTSA.2008.4530808</identifier><language>eng</language><publisher>IEEE</publisher><subject>Educational institutions ; Flash memory ; Implants ; Lithography ; Manufacturing ; Plugs ; Rails ; Robustness ; Space technology ; Tungsten</subject><ispartof>2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.81-82</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4530808$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,782,786,791,792,2060,27932,54927</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4530808$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Fastow, R.</creatorcontrib><creatorcontrib>Banerjee, R.</creatorcontrib><creatorcontrib>Bjeletich, P.</creatorcontrib><creatorcontrib>Brand, A.</creatorcontrib><creatorcontrib>Chao, H.</creatorcontrib><creatorcontrib>Gorman, J.</creatorcontrib><creatorcontrib>Guo, X.</creatorcontrib><creatorcontrib>Heng, J.B.</creatorcontrib><creatorcontrib>Koenigsfeld, N.</creatorcontrib><creatorcontrib>Ma, S.</creatorcontrib><creatorcontrib>Masad, A.</creatorcontrib><creatorcontrib>Soss, S.</creatorcontrib><creatorcontrib>Woo, B.J.</creatorcontrib><title>A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications</title><title>2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)</title><addtitle>VTSA</addtitle><description>A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm 2 . The cell size of 0.024μm 2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and excellent cycling behavior.</description><subject>Educational institutions</subject><subject>Flash memory</subject><subject>Implants</subject><subject>Lithography</subject><subject>Manufacturing</subject><subject>Plugs</subject><subject>Rails</subject><subject>Robustness</subject><subject>Space technology</subject><subject>Tungsten</subject><issn>1524-766X</issn><issn>2690-8174</issn><isbn>1424416140</isbn><isbn>9781424416141</isbn><isbn>9781424416158</isbn><isbn>1424416159</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9z09OhDAUgPH6L5HROYBx8y4AvpYCZUmIEzfOJEKMu0nDlKH6KISiZjybZ_BMbsatq2_xW32M3XCMOMf87rmuikggqkgmMSpUJ2yZZ4pLISVPeaJOWSDSHEPFM3nGFn8g8ZwFPBEyzNL05ZItvH9FFJjEWcDeCpCJ62G9eYIVad9BbZrODTTsD_Bp5w4qQ21YkN07s4NycLNuZg_a7QAjFPLnuxdQGiKo7JeBdpjg8Z1mG5L5MATFOJJt9GwH56_ZRavJm-WxV-x2dV-XD6E1xmzHyfZ6OmyPc_H_-guTv0x8</recordid><startdate>200804</startdate><enddate>200804</enddate><creator>Fastow, R.</creator><creator>Banerjee, R.</creator><creator>Bjeletich, P.</creator><creator>Brand, A.</creator><creator>Chao, H.</creator><creator>Gorman, J.</creator><creator>Guo, X.</creator><creator>Heng, J.B.</creator><creator>Koenigsfeld, N.</creator><creator>Ma, S.</creator><creator>Masad, A.</creator><creator>Soss, S.</creator><creator>Woo, B.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200804</creationdate><title>A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications</title><author>Fastow, R. ; Banerjee, R. ; Bjeletich, P. ; Brand, A. ; Chao, H. ; Gorman, J. ; Guo, X. ; Heng, J.B. ; Koenigsfeld, N. ; Ma, S. ; Masad, A. ; Soss, S. ; Woo, B.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_45308083</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Educational institutions</topic><topic>Flash memory</topic><topic>Implants</topic><topic>Lithography</topic><topic>Manufacturing</topic><topic>Plugs</topic><topic>Rails</topic><topic>Robustness</topic><topic>Space technology</topic><topic>Tungsten</topic><toplevel>online_resources</toplevel><creatorcontrib>Fastow, R.</creatorcontrib><creatorcontrib>Banerjee, R.</creatorcontrib><creatorcontrib>Bjeletich, P.</creatorcontrib><creatorcontrib>Brand, A.</creatorcontrib><creatorcontrib>Chao, H.</creatorcontrib><creatorcontrib>Gorman, J.</creatorcontrib><creatorcontrib>Guo, X.</creatorcontrib><creatorcontrib>Heng, J.B.</creatorcontrib><creatorcontrib>Koenigsfeld, N.</creatorcontrib><creatorcontrib>Ma, S.</creatorcontrib><creatorcontrib>Masad, A.</creatorcontrib><creatorcontrib>Soss, S.</creatorcontrib><creatorcontrib>Woo, B.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fastow, R.</au><au>Banerjee, R.</au><au>Bjeletich, P.</au><au>Brand, A.</au><au>Chao, H.</au><au>Gorman, J.</au><au>Guo, X.</au><au>Heng, J.B.</au><au>Koenigsfeld, N.</au><au>Ma, S.</au><au>Masad, A.</au><au>Soss, S.</au><au>Woo, B.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications</atitle><btitle>2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)</btitle><stitle>VTSA</stitle><date>2008-04</date><risdate>2008</risdate><spage>81</spage><epage>82</epage><pages>81-82</pages><issn>1524-766X</issn><eissn>2690-8174</eissn><isbn>1424416140</isbn><isbn>9781424416141</isbn><eisbn>9781424416158</eisbn><eisbn>1424416159</eisbn><abstract>A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm 2 . The cell size of 0.024μm 2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and excellent cycling behavior.</abstract><pub>IEEE</pub><doi>10.1109/VTSA.2008.4530808</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1524-766X |
| ispartof | 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.81-82 |
| issn | 1524-766X 2690-8174 |
| language | eng |
| recordid | cdi_ieee_primary_4530808 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Educational institutions Flash memory Implants Lithography Manufacturing Plugs Rails Robustness Space technology Tungsten |
| title | A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024μm2 Cell Size for Multi-level Applications |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-04T01%3A51%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%2045nm%20NOR%20Flash%20Technology%20with%20Self-Aligned%20Contacts%20and%200.024%CE%BCm2%20Cell%20Size%20for%20Multi-level%20Applications&rft.btitle=2008%20International%20Symposium%20on%20VLSI%20Technology,%20Systems%20and%20Applications%20(VLSI-TSA)&rft.au=Fastow,%20R.&rft.date=2008-04&rft.spage=81&rft.epage=82&rft.pages=81-82&rft.issn=1524-766X&rft.eissn=2690-8174&rft.isbn=1424416140&rft.isbn_list=9781424416141&rft_id=info:doi/10.1109/VTSA.2008.4530808&rft_dat=%3Cieee_6IE%3E4530808%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424416158&rft.eisbn_list=1424416159&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4530808&rfr_iscdi=true |