Sorter-based sigma-delta domain arithmetic circuits

This paper describes adder and multiplier circuits operating directly on first-order multi-level and second-order binary sigma-delta modulated signals. We first show that binary sorting networks with delayed feedback loops can be used as discrete variable digital sigma-delta modulators. We then build the adders based on the sorting networks. The circuit design scheme for the adder is independent of quantization spacing and the number of inputs. We build the multiplier simply by using the adders and exclusive-OR gates. The adders and the multipliers can be built of smaller number of logic gates and perform more precise arithmetic operation at a high oversampling ratio than multi-bit Nyquist rate circuits.