IBM z10: The Next-Generation Mainframe Microprocessor

IBM z10: The Next-Generation Mainframe Microprocessor

The IBM system z10 includes four microprocessor cores - each with a private 3-Mbyte cache - and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor s...

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Veröffentlicht in:IEEE MICRO 2008-03, Vol.28 (2), p.19-29
1. Verfasser: Webb, C.F.
Format: Artikel
Sprache:eng
Schlagworte:
Acceleration
Accelerators
branch prediction
Cache
Central processing units
Computer architecture
Cryptography
Data compression
decimal floating-point
Design engineering
Fabrics
Floating point arithmetic
Hardware
High performance computing
high-frequency design
Hot Chips 19
mainframe
Mainframes
microprocessor
Microprocessors
pipeline
Pipelines
Reduced instruction set computing
reliability
Semiconductors
Switches
symmetric multiprocessor (SMP)
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Beschreibung
Zusammenfassung:The IBM system z10 includes four microprocessor cores - each with a private 3-Mbyte cache - and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2008.26