Effect of noise on timing or data-pattern dependent delay variation when transmission-line effects are taken into account for on-chip wiring

Effect of noise on timing or data-pattern dependent delay variation when transmission-line effects are taken into account for on-chip wiring

The impact of data-pattern variation on timing for on-chip interconnect timing is investigated for typical local, global, and clock wiring. The validity of the methodology to combine noise and timing engines is benchmarked against accurate non-linear simulations with R(f)L(f)C circuit representation...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Deutsch, A., Smith, H.H., Vakirtzis, C., Kozhaya, J., Greenberg, L.M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Crosstalk
Delay effects
Frequency
Integrated circuit interconnections
Propagation delay
Timing
Transmission lines
Wires
Wiring
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The impact of data-pattern variation on timing for on-chip interconnect timing is investigated for typical local, global, and clock wiring. The validity of the methodology to combine noise and timing engines is benchmarked against accurate non-linear simulations with R(f)L(f)C circuit representation and recommendations for CAD tool development are given.
DOI:10.1109/SPI.2007.4512194