An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers

This paper presents a cost effective Embedded Test Circuit (ETC) for single ended Low Noise Amplifiers (LNAs). The ETC operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amplitude (gain reduction). The ETC along with a single ended LNA have been designed in a 0.35 μm CMOS technology to evaluate the efficiency of the proposed approach and experimental results are presented.