Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation
In this paper, we show the electrical characteristics of TSV (Through Silicon Via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO 2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon...
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| creator | Jun So Pak Chunghyun Ryu Kim, Joungho |
| description | In this paper, we show the electrical characteristics of TSV (Through Silicon Via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO 2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon resistivity in case of single silicon substrate. And we also show X-talk characteristics of two TSVs depending on distance of two signal TSVs and different locations of two signal TSVs and two ground TSVs in array type arrangement of TSV. Additionally, we show the electrical characteristics of TSV depending on number of stacked TSVs. All electrical characterizations on this paper are obtained using commercial 3-D full wave simulator and spice type circuit simulator such as HFSS of Ansoft Corporation and ADS of Agilent Corporation, respectively. |
| doi_str_mv | 10.1109/EMAP.2007.4510331 |
| format | Conference Proceeding |
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And we also show X-talk characteristics of two TSVs depending on distance of two signal TSVs and different locations of two signal TSVs and two ground TSVs in array type arrangement of TSV. Additionally, we show the electrical characteristics of TSV depending on number of stacked TSVs. All electrical characterizations on this paper are obtained using commercial 3-D full wave simulator and spice type circuit simulator such as HFSS of Ansoft Corporation and ADS of Agilent Corporation, respectively.</description><identifier>ISBN: 9781424419098</identifier><identifier>ISBN: 1424419093</identifier><identifier>EISBN: 1424419107</identifier><identifier>EISBN: 9781424419104</identifier><identifier>DOI: 10.1109/EMAP.2007.4510331</identifier><identifier>LCCN: 2007908976</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; Electric variables ; Electronics packaging ; Integrated circuit interconnections ; Power supplies ; Semiconductor device packaging ; Silicon ; Structural engineering ; Substrates ; Through-silicon vias</subject><ispartof>2007 International Conference on Electronic Materials and Packaging, 2007, p.1-6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4510331$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4510331$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jun So Pak</creatorcontrib><creatorcontrib>Chunghyun Ryu</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><title>Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation</title><title>2007 International Conference on Electronic Materials and Packaging</title><addtitle>EMAP</addtitle><description>In this paper, we show the electrical characteristics of TSV (Through Silicon Via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO 2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon resistivity in case of single silicon substrate. And we also show X-talk characteristics of two TSVs depending on distance of two signal TSVs and different locations of two signal TSVs and two ground TSVs in array type arrangement of TSV. Additionally, we show the electrical characteristics of TSV depending on number of stacked TSVs. All electrical characterizations on this paper are obtained using commercial 3-D full wave simulator and spice type circuit simulator such as HFSS of Ansoft Corporation and ADS of Agilent Corporation, respectively.</description><subject>Circuit simulation</subject><subject>Electric variables</subject><subject>Electronics packaging</subject><subject>Integrated circuit interconnections</subject><subject>Power supplies</subject><subject>Semiconductor device packaging</subject><subject>Silicon</subject><subject>Structural engineering</subject><subject>Substrates</subject><subject>Through-silicon vias</subject><isbn>9781424419098</isbn><isbn>1424419093</isbn><isbn>1424419107</isbn><isbn>9781424419104</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1OwzAQhI1QJWjpAyAuPsKhYZ04cXysSvmRikCi4lpt7E1rlKSVkxTBE_DYuNC9rGY0-lazjF0KiIQAfTt_nr5GMYCKZCogScQJGwoZSym0AHXKxlrlRw06H7DhIash1yo7Y-O2_YAwMk3yND5nP_OKTOedwYqbDXo0HXn3jZ3bNnxb8s5v-_WGt65yJjh7h_x6-fZ-wy3tqLGuWfNgt53vTdf7AMHG8hoPkCB2AVhTEC0vsCV7yCZ3vOyrin_ingK37qu_YxdsUGLV0vi4R2x5P1_OHieLl4en2XQxcRq6ic3AZKVWcZmbGOLcFBJBo0yxiKGwoVaKREoRFpnMCgJbIhZoU6kwNRqTEbv6xzoiWu28q9F_rY6PTH4B8GRn9g</recordid><startdate>200711</startdate><enddate>200711</enddate><creator>Jun So Pak</creator><creator>Chunghyun Ryu</creator><creator>Kim, Joungho</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200711</creationdate><title>Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation</title><author>Jun So Pak ; Chunghyun Ryu ; Kim, Joungho</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d60c6f972f8c2028cb4a09a45ab20bd0455aee77eab646be0dfaabad547a5c9a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Circuit simulation</topic><topic>Electric variables</topic><topic>Electronics packaging</topic><topic>Integrated circuit interconnections</topic><topic>Power supplies</topic><topic>Semiconductor device packaging</topic><topic>Silicon</topic><topic>Structural engineering</topic><topic>Substrates</topic><topic>Through-silicon vias</topic><toplevel>online_resources</toplevel><creatorcontrib>Jun So Pak</creatorcontrib><creatorcontrib>Chunghyun Ryu</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jun So Pak</au><au>Chunghyun Ryu</au><au>Kim, Joungho</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation</atitle><btitle>2007 International Conference on Electronic Materials and Packaging</btitle><stitle>EMAP</stitle><date>2007-11</date><risdate>2007</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><isbn>9781424419098</isbn><isbn>1424419093</isbn><eisbn>1424419107</eisbn><eisbn>9781424419104</eisbn><abstract>In this paper, we show the electrical characteristics of TSV (Through Silicon Via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO 2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon resistivity in case of single silicon substrate. And we also show X-talk characteristics of two TSVs depending on distance of two signal TSVs and different locations of two signal TSVs and two ground TSVs in array type arrangement of TSV. Additionally, we show the electrical characteristics of TSV depending on number of stacked TSVs. All electrical characterizations on this paper are obtained using commercial 3-D full wave simulator and spice type circuit simulator such as HFSS of Ansoft Corporation and ADS of Agilent Corporation, respectively.</abstract><pub>IEEE</pub><doi>10.1109/EMAP.2007.4510331</doi><tpages>6</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation Electric variables Electronics packaging Integrated circuit interconnections Power supplies Semiconductor device packaging Silicon Structural engineering Substrates Through-silicon vias |
| title | Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation |
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