Design and performance evaluation of a reconfigurable Delta MIN for MPSOC
Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry fo...
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| creator | Aydi, Y. Meftali, S. Dekeyser, J.-L. Abid, M. |
| description | Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to an on-chip communication. This paper presents the design of reconfigurable Delta MINs in which the connections change dynamically at run time. Using SystemC timed simulations, performance evaluation of a Delta MINs are given and analyzed. |
| doi_str_mv | 10.1109/ICM.2007.4497674 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4497674</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4497674</ieee_id><sourcerecordid>4497674</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-ded42b5ab2ccd1254fd376d7e491ce70ee62749b0cca6c57d83078a5e300dc0e3</originalsourceid><addsrcrecordid>eNo1kEFLw0AUhFe0YFt7F7zsH0h9u_t2N3uU1GqgtYK9l83uS4mkSUlSwX9vxToMDHP45jCM3QuYCwHuMc_Wcwlg54jOGotXbOZsKlAiihStumaT_2LEDRtLoV0ijIERm_xy7mypbtms7z_hLNQqRT1m-YL6at9w30R-pK5su4NvAnH68vXJD1Xb8LbknncU2qas9qfOFzXxBdWD5-v8jZ8Jvn7_2GR3bFT6uqfZJadsu3zeZq_JavOSZ0-rpHIwJJEiykL7QoYQhdRYRmVNtIROBLJAZKRFV0AI3gRtY6rApl6TAogBSE3Zw99sRUS7Y1cdfPe9u7yifgB75lCr</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Design and performance evaluation of a reconfigurable Delta MIN for MPSOC</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Aydi, Y. ; Meftali, S. ; Dekeyser, J.-L. ; Abid, M.</creator><creatorcontrib>Aydi, Y. ; Meftali, S. ; Dekeyser, J.-L. ; Abid, M.</creatorcontrib><description>Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to an on-chip communication. This paper presents the design of reconfigurable Delta MINs in which the connections change dynamically at run time. Using SystemC timed simulations, performance evaluation of a Delta MINs are given and analyzed.</description><identifier>ISSN: 2159-1660</identifier><identifier>ISBN: 1424418461</identifier><identifier>ISBN: 9781424418466</identifier><identifier>EISBN: 9781424418473</identifier><identifier>EISBN: 142441847X</identifier><identifier>DOI: 10.1109/ICM.2007.4497674</identifier><identifier>LCCN: 2007907923</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Delay ; Delta MIN ; Design engineering ; MPSOC ; Multiprocessing systems ; Multiprocessor interconnection networks ; Network design ; Network topology ; Network-on-a-chip ; NOC ; Performance analysis ; Reconfigurable MIN ; Switches ; System-on-a-chip</subject><ispartof>2007 Internatonal Conference on Microelectronics, 2007, p.115-118</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4497674$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4497674$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Aydi, Y.</creatorcontrib><creatorcontrib>Meftali, S.</creatorcontrib><creatorcontrib>Dekeyser, J.-L.</creatorcontrib><creatorcontrib>Abid, M.</creatorcontrib><title>Design and performance evaluation of a reconfigurable Delta MIN for MPSOC</title><title>2007 Internatonal Conference on Microelectronics</title><addtitle>ICM</addtitle><description>Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to an on-chip communication. This paper presents the design of reconfigurable Delta MINs in which the connections change dynamically at run time. Using SystemC timed simulations, performance evaluation of a Delta MINs are given and analyzed.</description><subject>Analytical models</subject><subject>Delay</subject><subject>Delta MIN</subject><subject>Design engineering</subject><subject>MPSOC</subject><subject>Multiprocessing systems</subject><subject>Multiprocessor interconnection networks</subject><subject>Network design</subject><subject>Network topology</subject><subject>Network-on-a-chip</subject><subject>NOC</subject><subject>Performance analysis</subject><subject>Reconfigurable MIN</subject><subject>Switches</subject><subject>System-on-a-chip</subject><issn>2159-1660</issn><isbn>1424418461</isbn><isbn>9781424418466</isbn><isbn>9781424418473</isbn><isbn>142441847X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kEFLw0AUhFe0YFt7F7zsH0h9u_t2N3uU1GqgtYK9l83uS4mkSUlSwX9vxToMDHP45jCM3QuYCwHuMc_Wcwlg54jOGotXbOZsKlAiihStumaT_2LEDRtLoV0ijIERm_xy7mypbtms7z_hLNQqRT1m-YL6at9w30R-pK5su4NvAnH68vXJD1Xb8LbknncU2qas9qfOFzXxBdWD5-v8jZ8Jvn7_2GR3bFT6uqfZJadsu3zeZq_JavOSZ0-rpHIwJJEiykL7QoYQhdRYRmVNtIROBLJAZKRFV0AI3gRtY6rApl6TAogBSE3Zw99sRUS7Y1cdfPe9u7yifgB75lCr</recordid><startdate>200712</startdate><enddate>200712</enddate><creator>Aydi, Y.</creator><creator>Meftali, S.</creator><creator>Dekeyser, J.-L.</creator><creator>Abid, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200712</creationdate><title>Design and performance evaluation of a reconfigurable Delta MIN for MPSOC</title><author>Aydi, Y. ; Meftali, S. ; Dekeyser, J.-L. ; Abid, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-ded42b5ab2ccd1254fd376d7e491ce70ee62749b0cca6c57d83078a5e300dc0e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Analytical models</topic><topic>Delay</topic><topic>Delta MIN</topic><topic>Design engineering</topic><topic>MPSOC</topic><topic>Multiprocessing systems</topic><topic>Multiprocessor interconnection networks</topic><topic>Network design</topic><topic>Network topology</topic><topic>Network-on-a-chip</topic><topic>NOC</topic><topic>Performance analysis</topic><topic>Reconfigurable MIN</topic><topic>Switches</topic><topic>System-on-a-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Aydi, Y.</creatorcontrib><creatorcontrib>Meftali, S.</creatorcontrib><creatorcontrib>Dekeyser, J.-L.</creatorcontrib><creatorcontrib>Abid, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Aydi, Y.</au><au>Meftali, S.</au><au>Dekeyser, J.-L.</au><au>Abid, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design and performance evaluation of a reconfigurable Delta MIN for MPSOC</atitle><btitle>2007 Internatonal Conference on Microelectronics</btitle><stitle>ICM</stitle><date>2007-12</date><risdate>2007</risdate><spage>115</spage><epage>118</epage><pages>115-118</pages><issn>2159-1660</issn><isbn>1424418461</isbn><isbn>9781424418466</isbn><eisbn>9781424418473</eisbn><eisbn>142441847X</eisbn><abstract>Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to an on-chip communication. This paper presents the design of reconfigurable Delta MINs in which the connections change dynamically at run time. Using SystemC timed simulations, performance evaluation of a Delta MINs are given and analyzed.</abstract><pub>IEEE</pub><doi>10.1109/ICM.2007.4497674</doi><tpages>4</tpages></addata></record> |
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| issn | 2159-1660 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models Delay Delta MIN Design engineering MPSOC Multiprocessing systems Multiprocessor interconnection networks Network design Network topology Network-on-a-chip NOC Performance analysis Reconfigurable MIN Switches System-on-a-chip |
| title | Design and performance evaluation of a reconfigurable Delta MIN for MPSOC |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T12%3A15%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Design%20and%20performance%20evaluation%20of%20a%20reconfigurable%20Delta%20MIN%20for%20MPSOC&rft.btitle=2007%20Internatonal%20Conference%20on%20Microelectronics&rft.au=Aydi,%20Y.&rft.date=2007-12&rft.spage=115&rft.epage=118&rft.pages=115-118&rft.issn=2159-1660&rft.isbn=1424418461&rft.isbn_list=9781424418466&rft_id=info:doi/10.1109/ICM.2007.4497674&rft_dat=%3Cieee_6IE%3E4497674%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424418473&rft.eisbn_list=142441847X&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4497674&rfr_iscdi=true |