Design and performance evaluation of a reconfigurable Delta MIN for MPSOC

Design and performance evaluation of a reconfigurable Delta MIN for MPSOC

Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry fo...

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Bibliographische Detailangaben
Hauptverfasser: Aydi, Y., Meftali, S., Dekeyser, J.-L., Abid, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Delay
Delta MIN
Design engineering
MPSOC
Multiprocessing systems
Multiprocessor interconnection networks
Network design
Network topology
Network-on-a-chip
NOC
Performance analysis
Reconfigurable MIN
Switches
System-on-a-chip
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Beschreibung
Zusammenfassung:Multiprocessor system on chip is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to an on-chip communication. This paper presents the design of reconfigurable Delta MINs in which the connections change dynamically at run time. Using SystemC timed simulations, performance evaluation of a Delta MINs are given and analyzed.
ISSN:2159-1660
DOI:10.1109/ICM.2007.4497674