The wafer preparation technology with nano size particle contamination by using single spin processor

In LSI manufacturing industry, design rule shrinkage is accelerated, also contamination control in cleaning process is required as nanometer order. Especially, wet cleaning process needs to solve two issues, one is PR stripping and lower film loss at particle removal[1,2]. As for such washing technology development, it was advanced a polluted wafer as a sample in a PSL (Poly Styrene Latex) particle historically. It is important for the washing evaluation using a particle forcible contamination wafer, and its development to carry out with the optimal sample for these issues. The particle containing Si is practical from the trend of a future device material and also in high temperature SPM process development. It is thermally stable compared with PSL in hot SPM, and excels as an index of future evaluation. This paper reports the Si 3 N 4 particle contaminating wafer preparation technology of controlling 65 nm order with sufficient linearity by using Single Spin processor.