Pipelining high-radix SRT division algorithms
This paper shows various ways to pipeline popular SRT division algorithms. Different logic gate families and circuit structures are used to explore possible overheads introduced in each implementation. Simulation results are compared to find out the fastest possible architecture and comparisons are...
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| creator | Upadhyay, S. Stine, J.E. |
| description | This paper shows various ways to pipeline popular SRT division algorithms. Different logic gate families and circuit structures are used to explore possible overheads introduced in each implementation. Simulation results are compared to find out the fastest possible architecture and comparisons are explored from parasitically extracted AMI C5N 0.5 mum layouts. |
| doi_str_mv | 10.1109/MWSCAS.2007.4488595 |
| format | Conference Proceeding |
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| ispartof | 2007 50th Midwest Symposium on Circuits and Systems, 2007, p.309-312 |
| issn | 1548-3746 1558-3899 |
| language | eng |
| recordid | cdi_ieee_primary_4488595 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Ambient intelligence CMOS logic circuits CMOS technology Computational modeling Hardware Latches Logic circuits Logic gates Pipeline processing |
| title | Pipelining high-radix SRT division algorithms |
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