A High Performance 1μm CMOS Process for VLSI Applications

A High Performance 1μm CMOS Process for VLSI Applications

Feature sizes on circuits for logic and memory applications are rapidly approaching the one micron level. We have developed a lμm CMOS process that uses only seven photolithography steps (including protective overcoat) and has sheet resistivities of less than 1 ohm/sq. for both moat and gate interco...

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Bibliographische Detailangaben
Hauptverfasser: Doering, R. R., Duane, M. P., McDavid, J. M., Baglee, D. A., Clark, D., Crank, S., Armstrong, G. J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Aluminum
CMOS logic circuits
CMOS process
Conductivity
Implants
Integrated circuit interconnections
Silicides
Titanium
Tungsten
Very large scale integration
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Beschreibung
Zusammenfassung:Feature sizes on circuits for logic and memory applications are rapidly approaching the one micron level. We have developed a lμm CMOS process that uses only seven photolithography steps (including protective overcoat) and has sheet resistivities of less than 1 ohm/sq. for both moat and gate interconnects.