High Aspect Ratio Vias First for Advanced Packaging

In this paper a new 'via-first' technology which is compatible with CMOS high temperature steps will be presented. This technology is based on filling high aspect ratio trenches with doped polysilicon and thinning the silicon after active device bonding onto a wafer carrier. The initial morphological requirements are described and different designs of TSV are presented. The complete technology for TSV achievement is described in detail and electrical results obtained with different vias geometries are presented and compared to initial calculations. Finally, several reflows experiments have been performed on these vias and electrical measurements have been achieved again and compared to initial results.