FPGA Design of Digital Codec for Passive RFID Tag

This paper presents the design and implementation of digital Codec for a passive RFID tags based on a robust mutual authentication protocol. The proposed protocol is based on a three-way challenge response authentication scheme between a back-end server and RFID tags which modifies the ISO/IEC 18000...

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Bibliographische Detailangaben
Hauptverfasser:	Ryu, Su-Bong, Jeon, Jin-Oh, Kang, Min-Sup
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Authentication Codecs digital processorRFID tagSHA-1extended authentication protocolthree-way challenge response authenticationFPGA implementation Field programmable gate arrays Hardware design languages IEC standards ISO standards Passive RFID tags Protocols RFID tags Robustness
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Beschreibung
Zusammenfassung:	This paper presents the design and implementation of digital Codec for a passive RFID tags based on a robust mutual authentication protocol. The proposed protocol is based on a three-way challenge response authentication scheme between a back-end server and RFID tags which modifies the ISO/IEC 18000-3 standard.The digital Codec based on the proposed protocol was described using Verilog HDL at the Behavioral level, and it operates at a clock frequency of 75 MHz on Xilinx-VirtexII XC2V8000 FPGA device.
DOI:	10.1109/ALPIT.2007.99