Technology and Performance of InAlN/AlN/GaN HEMTs With Gate Insulation and Current Collapse Suppression Using Zr \hbox or Hf \hbox

We present the technology and performance of InAlN/AlN/GaN MOS HEMTs with gate insulation and surface passivation using Zr or Hf . About 10-nm-thick high- dielectrics were deposited by MOCVD before the ohmic contact processing. Plasma pretreatment allowed the reduction of the temperature of the ohmi...

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Veröffentlicht in:IEEE transactions on electron devices 2008-03, Vol.55 (3), p.937-941
Hauptverfasser: Kuzmik, J., Pozzovivo, G., Abermann, S., Carlin, J.-F., Gonschorek, M., Feltin, E., Grandjean, N., Bertagnolli, E., Strasser, G., Pogany, D.
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Sprache:eng
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Zusammenfassung:We present the technology and performance of InAlN/AlN/GaN MOS HEMTs with gate insulation and surface passivation using Zr or Hf . About 10-nm-thick high- dielectrics were deposited by MOCVD before the ohmic contact processing. Plasma pretreatment allowed the reduction of the temperature of the ohmic contact annealing at 600degC. The insulation and passivation of 2-m gate-length MOS HEMTs lead to a gate leakage current reduction by four orders of magnitude and a 2.5 increase of the pulsed drain-current if compared with a Schottky barrier (SB) HEMT. A dc characterization shows 110 mS mm transconductance and 0.9 A mm drain--currents that represent improvements in comparison to the similar SB HEMT and that is explained by a mobility-dependent carrier depletion effect.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2007.915089