A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltag...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2008-01, Vol.43 (1), p.172-179
Hauptverfasser:	Yih Wang, Hong Jo Ahn, Bhattacharya, U., Zhanping Chen, Coan, T., Hamzaoglu, F., Hafez, W.M., Chia-Hong Jan, Kolar, P., Kulkarni, S.H., Jie-Feng Lin, Yong-Gee Ng, Post, I., Liqiong Wei, Ying Zhang, Zhang, K., Bohr, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Central Processing Unit CMOS logic circuits CMOS technology Costs Energy consumption Integrated circuit technology Logic design Low-power memory MOS memory integrated circuits Random access memory Silicon sleep transistor static random-access memory (SRAM) Voltage
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