A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltag...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2008-01, Vol.43 (1), p.172-179 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Yih Wang Hong Jo Ahn Bhattacharya, U. Zhanping Chen Coan, T. Hamzaoglu, F. Hafez, W.M. Chia-Hong Jan Kolar, P. Kulkarni, S.H. Jie-Feng Lin Yong-Gee Ng Post, I. Liqiong Wei Ying Zhang Zhang, K. Bohr, M. |
| description | A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum 2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes. |
| doi_str_mv | 10.1109/JSSC.2007.907996 |
| format | Article |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Central Processing Unit CMOS logic circuits CMOS technology Costs Energy consumption Integrated circuit technology Logic design Low-power memory MOS memory integrated circuits Random access memory Silicon sleep transistor static random-access memory (SRAM) Voltage |
| title | A 1.1 GHz 12 \muA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications |
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