A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13 mu m CMOS technology, sixteen 800 MHz data-parallel...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2008-01, Vol.43 (1), p.202-213
Hauptverfasser:	Khailany, B.K., Williams, T., Lin, J., Long, E.P., Rygh, M., Tovey, D.W., Dally, W.J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit properties Circuits Clocks CMOS CMOS technology Design. Technologies. Operation analysis. Testing Digital circuits Digital signal processing Digital signal processor (DSP) Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology H.264 Image coding Integrated circuits Integrated circuits by function (including memories and processors) Lanes Microprocessors Parallel processing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing stream processing Streaming media Streams System on chip System-on-a-chip Throughput Transistors video encoding VLIW
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Beschreibung
Zusammenfassung:	A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13 mu m CMOS technology, sixteen 800 MHz data-parallel lanes combine to deliver performance of 512 8-bit GOPS or 256 16-bit GOPS, or 128 billion 16-bit multiply-accumulates per second GMACs), with a power efficiency of 82 pJ/MAC.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2007.909331