A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS

A fully differential CDR circuit realized in 0.18-mum CMOS technology targeted for the ONU in GPON applications at 2.5 Gb/s is presented. The CDR demonstrates very low RMS jitter of 1.4 psec, along with a acquisition range of 220 MHz employing a simple PLL architecture without a need for any frequency acquisition aid or external reference. The LC VCO employs complementary varactor structure for differential tuning enabling the CDR to function with noisy power supplies. The CDR performs well even when there is no bit transition (Consecutive Identical Digits or CID) for 400 bits in a 2 11 -1 PRBS sequence. The core clock recovery circuit consumes 14.5 mA from 1.8 V power supply. The noise immunity, jitter tolerance and jitter generation of the proposed CDR outperforms a similar CDR with single tuned VCO of same gain and loop bandwidth.