Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction

Power switch transistors are very effective in cutting leakage currents of digital circuits in standby mode. Moreover, among the existing power switch transistors, SCCMOS is the most suited to a low-VDD environment since it uses a Iow-V TH transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. We have therefore designed and fabricated a polarization circuit that automatically finds the optimal bias voltage whatever the environment conditions. This circuit, realized in STMicroelectronics bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature.