Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits
Energy dissipation, performance, and voltage scaling of Multi-Gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10 k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at V DD =1....
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| creator | Pacha, C. von Arnim, K. Bauer, F. Schulz, T. Xiong, W. San, K.T. Marshall, A. Baumann, T. Cleavelin, C.-R. Schruefer, K. Berthold, J. |
| description | Energy dissipation, performance, and voltage scaling of Multi-Gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10 k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at V DD =1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control. |
| doi_str_mv | 10.1109/ESSCIRC.2007.4430258 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1930-8833 |
| ispartof | ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007, p.111-114 |
| issn | 1930-8833 2643-1319 |
| language | eng |
| recordid | cdi_ieee_primary_4430258 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit analysis Circuit testing Clocks CMOS technology Energy dissipation FETs Frequency Performance analysis Scalability Voltage |
| title | Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits |
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