Two-level tiling for MPSoC architecture

Multiprocessor systems-on-a-chip (MPSoCs architectures) have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of several level of memory hierarchy. Usually tiling is applied to one loop nest; in this paper we apply simultaneously loop fusion with two-level tiling to several loop nests in the context of a MPSoC architecture. The two level-tiling allows the simultaneous optimization of caches and registers. To optimize the memory space used by temporary arrays, buffers and registers are used as a replacement. The experiments show that these techniques yield a significant reduction in the number of data cache misses and in processing time.