A high-performance VLSI architecture for CABAC decoding in H.264/AVC

A mixed hardware/software architecture for CABAC decoding in H.264/AVC is proposed in this paper. For the purpose of flexibility, ctxldx calculation process is implemented by software, while others are implemented by hardware. An optimized parallel decoding architecture that allows decoding two binary symbols at one clock cycle is designed to enhance overall decoding performance. An efficient scheme of accessing context models is presented. Experimental results show that the proposed architecture improves the decoding performance by 20% compared to conventional scheme. The proposed design can achieve HDTV 1080i video processing requirement when operated at 140 MHz.