A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders

A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders

This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algori...

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Bibliographische Detailangaben
Hauptverfasser: Chi-Hong Chan, Cheong-Fat Chan, Chiu-Sing Choy, Kong-Pang Pun
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Adders
CMOS logic circuits
CMOS process
CMOS technology
Error correction
Integrated circuit interconnections
Modems
Quantization
Sampling methods
Voltage
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Beschreibung
Zusammenfassung:This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.
ISSN:2162-7541
2162-755X
DOI:10.1109/ICASIC.2007.4415623