A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems

In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 μ m CMOS technology and the total circuit area is 480 μ m 2 . Measurement results show that the circuit functions correctly at a wide range of supply volta...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yu-Shiang Lin, Sylvester, D., Blaauw, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit testing CMOS technology Gate leakage Monitoring MOS capacitors Particle measurements Power dissipation Semiconductor device measurement Temperature sensors Voltage
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