A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems

A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems

In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 μ m CMOS technology and the total circuit area is 480 μ m 2 . Measurement results show that the circuit functions correctly at a wide range of supply volta...

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Bibliographische Detailangaben
Hauptverfasser: Yu-Shiang Lin, Sylvester, D., Blaauw, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit testing
CMOS technology
Gate leakage
Monitoring
MOS capacitors
Particle measurements
Power dissipation
Semiconductor device measurement
Temperature sensors
Voltage
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Beschreibung
Zusammenfassung:In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 μ m CMOS technology and the total circuit area is 480 μ m 2 . Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300mV to 1.2V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/°C at 600mV and 0.6%/°C at 300mV. The power dissipation is less than 1pW running at 20°C and 300mV.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2007.4405761