8-bit AES Implementation in FPGA by Multiplexing 32-bit AES Operation

8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction- Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES...

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Bibliographische Detailangaben
Hauptverfasser: Chi-Jeng Chang, Chi-Wu Huang, Hung-Yun Tai, Mao-Yuan Lin
Format: Tagungsbericht
Sprache:eng
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