Architecture of the Scalable Communications Core's Network on Chip

Architecture of the Scalable Communications Core's Network on Chip

The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE MICRO 2007-09, Vol.27 (5), p.62-74
Hauptverfasser: Arditti Ilitzky, David, Hoffman, Jeffrey D., Chun, Anthony, Perez Esparza, Brando
Format: Artikel
Sprache:eng
Schlagworte:
Accelerators
Access protocols
Architecture
Baseband
Chips
communication
Computer architecture
Delay
Digital TV
Extensibility
Flexibility
Hardware
Microprocessors
multicore architectures
Network topologies
Network-on-a-chip
networking
Networks
on-chip interconnection networks
parallel architectures
Protocol
Protocol (computers)
Scalability
Throughput
wide-area networks
WiMAX
wireless
Wireless application protocol
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2007.4378784