Model for a CMOS Bit-Level Product Cell

An analysis method for a bit-level product cell used for vector-matrix multiplications is presented. The cell is a combination of a charge injection binary multiplier and an analog accumulator. CID/CCD principles help to understand the cell function and MOS structure equations are used to describe t...

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Hauptverfasser:	Gonzalez-Navarro, Y.E., Gomez-Castaneda, F., Moreno-Cadenas, J.A., Flores-Nava, L.M., Arellano-Cardenas, O.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CCD Charge coupled devices CID CMOS Computer architecture Encoding Equations MOS Neural networks product cell Semiconductor device modeling Solid modeling Solid state circuits Support vector machines vector-matrix multiplication (VMM) Very large scale integration
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Beschreibung
Zusammenfassung:	An analysis method for a bit-level product cell used for vector-matrix multiplications is presented. The cell is a combination of a charge injection binary multiplier and an analog accumulator. CID/CCD principles help to understand the cell function and MOS structure equations are used to describe the cell operations.
DOI:	10.1109/ICEEE.2007.4345046