A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS

A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS

A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, F s , to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabrica...

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Hauptverfasser: Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Soe, Z., Aytur, T., Ran-Hong Yan
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Capacitors
Chaos
Clocks
OFDM
Pipelines
reconfigurable
Sampling methods
Tellurium
time-interleaved pipeline ADC
Ultra wideband technology
Voltage
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Beschreibung
Zusammenfassung:A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, F s , to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume power of 92 mW from a 1.3 V supply.
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2007.4342768