A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices
Silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET...
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| creator | Lee, Hyunjin Kim, Ju-Hyun Bae, Dong-il Jeon, Sang Cheol Kim, Kwang Hee Lee, Gi Sung Oh, Jae Sub Park, Yun Chang Bae, Woo Ho Yoo, Jung Jae Yang, Jun Mo Ryu, Seong-Wan Lee, Hee Mok Choi, Yang-Kyu Han, Jin-Woo Yu, Lee-Eun Im, Maesoon Kim, Chungjin Kim, Sungho Lee, Eujune Kim, Kuk-Hwan |
| description | Silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/ crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45deg device rotation rather than 0deg. Utilizing an 7 nm spherical nanowire on the 8 nm SiNAWI-NVM with ONO structure, 1.7 V V T -window was achieved from 12 V/80 musec program conditions with retention enhancement. |
| doi_str_mv | 10.1109/VLSIT.2007.4339761 |
| format | Conference Proceeding |
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N-and P-channel SiNAWI-FET showed the highest driving current on (110)/ crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45deg device rotation rather than 0deg. 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N-and P-channel SiNAWI-FET showed the highest driving current on (110)/ crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45deg device rotation rather than 0deg. Utilizing an 7 nm spherical nanowire on the 8 nm SiNAWI-NVM with ONO structure, 1.7 V V T -window was achieved from 12 V/80 musec program conditions with retention enhancement.</description><subject>Fabrication</subject><subject>FinFETs</subject><subject>Logic devices</subject><subject>MOS devices</subject><subject>Nanoscale devices</subject><subject>Nanostructures</subject><subject>Nonvolatile memory</subject><subject>Scalability</subject><subject>Silicon</subject><subject>Very large scale integration</subject><issn>0743-1562</issn><isbn>4900784036</isbn><isbn>9784900784031</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMtOwzAURC0BEm3hB2DjH0i4znUeXlbl0UqhIBEqdpVjXxejPJATgfr3RKKL0ZyzmcUwdiMgFgLU3a5821RxApDHElHlmThjc6kmLyRgds5mkEuMRJoll2w-DF8ACaRYzNjHkm911__6QLwKuhv8MPaBuylrf_jkrxQmbnVniJf9wRuuO8srCrr2I9_2XbTrGz36hvgztX048nv68YaGK3bhdDPQ9akX7P3xoVqto_LlabNalpFPpBijwpGCDFNI6gQzMUmtRO6Es0ZORNahBWdrtEaljlJncmsKW4NAJVEUuGC3_7ueiPbfwbc6HPenF_APuMlR9Q</recordid><startdate>200706</startdate><enddate>200706</enddate><creator>Lee, Hyunjin</creator><creator>Kim, Ju-Hyun</creator><creator>Bae, Dong-il</creator><creator>Jeon, Sang Cheol</creator><creator>Kim, Kwang Hee</creator><creator>Lee, Gi Sung</creator><creator>Oh, Jae Sub</creator><creator>Park, Yun Chang</creator><creator>Bae, Woo Ho</creator><creator>Yoo, Jung Jae</creator><creator>Yang, Jun Mo</creator><creator>Ryu, Seong-Wan</creator><creator>Lee, Hee Mok</creator><creator>Choi, Yang-Kyu</creator><creator>Han, Jin-Woo</creator><creator>Yu, Lee-Eun</creator><creator>Im, Maesoon</creator><creator>Kim, Chungjin</creator><creator>Kim, Sungho</creator><creator>Lee, Eujune</creator><creator>Kim, Kuk-Hwan</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200706</creationdate><title>A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices</title><author>Lee, Hyunjin ; Kim, Ju-Hyun ; Bae, Dong-il ; Jeon, Sang Cheol ; Kim, Kwang Hee ; Lee, Gi Sung ; Oh, Jae Sub ; Park, Yun Chang ; Bae, Woo Ho ; Yoo, Jung Jae ; Yang, Jun Mo ; Ryu, Seong-Wan ; Lee, Hee Mok ; Choi, Yang-Kyu ; Han, Jin-Woo ; Yu, Lee-Eun ; Im, Maesoon ; Kim, Chungjin ; Kim, Sungho ; Lee, Eujune ; Kim, Kuk-Hwan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-8fe9063502b2361e90b917f1fdc4b91edf3d0fdb3dc95fe5fc7dc8db013943183</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Fabrication</topic><topic>FinFETs</topic><topic>Logic devices</topic><topic>MOS devices</topic><topic>Nanoscale devices</topic><topic>Nanostructures</topic><topic>Nonvolatile memory</topic><topic>Scalability</topic><topic>Silicon</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, Hyunjin</creatorcontrib><creatorcontrib>Kim, Ju-Hyun</creatorcontrib><creatorcontrib>Bae, Dong-il</creatorcontrib><creatorcontrib>Jeon, Sang Cheol</creatorcontrib><creatorcontrib>Kim, Kwang Hee</creatorcontrib><creatorcontrib>Lee, Gi Sung</creatorcontrib><creatorcontrib>Oh, Jae Sub</creatorcontrib><creatorcontrib>Park, Yun Chang</creatorcontrib><creatorcontrib>Bae, Woo Ho</creatorcontrib><creatorcontrib>Yoo, Jung Jae</creatorcontrib><creatorcontrib>Yang, Jun Mo</creatorcontrib><creatorcontrib>Ryu, Seong-Wan</creatorcontrib><creatorcontrib>Lee, Hee Mok</creatorcontrib><creatorcontrib>Choi, Yang-Kyu</creatorcontrib><creatorcontrib>Han, Jin-Woo</creatorcontrib><creatorcontrib>Yu, Lee-Eun</creatorcontrib><creatorcontrib>Im, Maesoon</creatorcontrib><creatorcontrib>Kim, Chungjin</creatorcontrib><creatorcontrib>Kim, Sungho</creatorcontrib><creatorcontrib>Lee, Eujune</creatorcontrib><creatorcontrib>Kim, Kuk-Hwan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Hyunjin</au><au>Kim, Ju-Hyun</au><au>Bae, Dong-il</au><au>Jeon, Sang Cheol</au><au>Kim, Kwang Hee</au><au>Lee, Gi Sung</au><au>Oh, Jae Sub</au><au>Park, Yun Chang</au><au>Bae, Woo Ho</au><au>Yoo, Jung Jae</au><au>Yang, Jun Mo</au><au>Ryu, Seong-Wan</au><au>Lee, Hee Mok</au><au>Choi, Yang-Kyu</au><au>Han, Jin-Woo</au><au>Yu, Lee-Eun</au><au>Im, Maesoon</au><au>Kim, Chungjin</au><au>Kim, Sungho</au><au>Lee, Eujune</au><au>Kim, Kuk-Hwan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices</atitle><btitle>2007 IEEE Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2007-06</date><risdate>2007</risdate><spage>144</spage><epage>145</epage><pages>144-145</pages><issn>0743-1562</issn><isbn>4900784036</isbn><isbn>9784900784031</isbn><abstract>Silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/ crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45deg device rotation rather than 0deg. Utilizing an 7 nm spherical nanowire on the 8 nm SiNAWI-NVM with ONO structure, 1.7 V V T -window was achieved from 12 V/80 musec program conditions with retention enhancement.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2007.4339761</doi><tpages>2</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Fabrication FinFETs Logic devices MOS devices Nanoscale devices Nanostructures Nonvolatile memory Scalability Silicon Very large scale integration |
| title | A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices |
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