Gate-all-around Twin Silicon nanowire SONOS Memory

Gate-all-around Twin Silicon nanowire SONOS Memory

We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at V d = 2 V, V g = 6 V and erase speed of 1 ms at V d = 4.5 V, V g = -6 V are achie...

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Hauptverfasser: Suk, Sung Dae, Yeo, Kyoung Hwan, Cho, Keun Hwi, Li, Ming, Yeoh, Yun young, Hong, Ki-Ha, Kim, Sung-Han, Koh, Young-Ho, Jung, Sunggon, Jang, WonJun, Kim, Dong-Won, Park, Donggun, Ryu, Byung-Il
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Channel hot electron injection
Hot carriers
Interference
Nanoscale devices
Nonvolatile memory
Photonic band gap
Research and development
Silicon compounds
SONOS devices
Tunneling
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Zusammenfassung:We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at V d = 2 V, V g = 6 V and erase speed of 1 ms at V d = 4.5 V, V g = -6 V are achieved with 2~3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on V th shift (DeltaV th ) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (d nw ) decreases, faster program speed and larger DeltaV th are observed.
ISSN:0743-1562
DOI:10.1109/VLSIT.2007.4339760