Multi-Gigabit I/O Link Circuit Design Challenges and Techniques
This paper describes the major challenges in designing multi-gigabit I/O link CMOS circuits. Techniques to overcome the challenges are presented, including transceiver design, discrete and continuous time equalization, termination control, and clocking circuits.
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| creator | Zuoguo Wu Peng Zou Dibene, J. Evelina Yeung Thenus, F. |
| description | This paper describes the major challenges in designing multi-gigabit I/O link CMOS circuits. Techniques to overcome the challenges are presented, including transceiver design, discrete and continuous time equalization, termination control, and clocking circuits. |
| doi_str_mv | 10.1109/ISEMC.2007.99 |
| format | Conference Proceeding |
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| identifier | ISSN: 2158-110X |
| ispartof | 2007 IEEE International Symposium on Electromagnetic Compatibility, 2007, p.1-5 |
| issn | 2158-110X 2158-1118 |
| language | eng |
| recordid | cdi_ieee_primary_4305679 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth Circuit synthesis Clocks Electrostatic discharge Integrated circuit interconnections Jitter Reflection Resistors Threshold voltage Timing |
| title | Multi-Gigabit I/O Link Circuit Design Challenges and Techniques |
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