Multi-Gigabit I/O Link Circuit Design Challenges and Techniques

Multi-Gigabit I/O Link Circuit Design Challenges and Techniques

This paper describes the major challenges in designing multi-gigabit I/O link CMOS circuits. Techniques to overcome the challenges are presented, including transceiver design, discrete and continuous time equalization, termination control, and clocking circuits.

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Bibliographische Detailangaben
Hauptverfasser: Zuoguo Wu, Peng Zou, Dibene, J., Evelina Yeung, Thenus, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Circuit synthesis
Clocks
Electrostatic discharge
Integrated circuit interconnections
Jitter
Reflection
Resistors
Threshold voltage
Timing
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Beschreibung
Zusammenfassung:This paper describes the major challenges in designing multi-gigabit I/O link CMOS circuits. Techniques to overcome the challenges are presented, including transceiver design, discrete and continuous time equalization, termination control, and clocking circuits.
ISSN:2158-110X
2158-1118
DOI:10.1109/ISEMC.2007.99