Three-dimensional TCAD Process and Device Simulations

Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench iso...

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Hauptverfasser: Avci, I., Balasingam, P., Sayed, K.E., Gharib, J., Johnson, M.D., Kells, K., Kiralyfalvi, G., Koltyzhenkov, V., Kucherov, A., Lyumkis, E., Penzin, O., Polsky, B., Rao, V., Simeonov, S.D., Strecker, N., Tan, Z., Villablanca, L., Fichtner, W.
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container_start_page 41
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container_volume
creator Avci, I.
Balasingam, P.
Sayed, K.E.
Gharib, J.
Johnson, M.D.
Kells, K.
Kiralyfalvi, G.
Koltyzhenkov, V.
Kucherov, A.
Lyumkis, E.
Penzin, O.
Polsky, B.
Rao, V.
Simeonov, S.D.
Strecker, N.
Tan, Z.
Villablanca, L.
Fichtner, W.
description Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.
doi_str_mv 10.1109/UGIM.2006.4286350
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4286350</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4286350</ieee_id><sourcerecordid>4286350</sourcerecordid><originalsourceid>FETCH-LOGICAL-i105t-59a4b1ab9491ca74b08c9662e35578e6f02632d1318841066ccdd919a70a238f3</originalsourceid><addsrcrecordid>eNo1kNtKw0AYhNcTGGseQLzJC2z897x7WdJaCxUF0-uy2fzBlSaVbBV8ewPWuZmL-RiGIeSOQckYuIftav1ccgBdSm61UHBGcmcsk1xK4Nqac5JxYRRVU3ZBbv4DA5ckAyMdnRhzTfKUPmCSVFIYmxFVv4-ItI09DikeBr8v6mq-KF7HQ8CUCj-0xQK_Y8DiLfZfe3-coHRLrjq_T5iffEa2j8u6eqKbl9W6mm9oZKCOVDkvG-YbJx0L3sgGbHBacxRKGYu6mwYK3jLBrJUMtA6hbR1z3oDnwnZiRu7_eiMi7j7H2PvxZ3d6QPwClbxIdg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Three-dimensional TCAD Process and Device Simulations</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Avci, I. ; Balasingam, P. ; Sayed, K.E. ; Gharib, J. ; Johnson, M.D. ; Kells, K. ; Kiralyfalvi, G. ; Koltyzhenkov, V. ; Kucherov, A. ; Lyumkis, E. ; Penzin, O. ; Polsky, B. ; Rao, V. ; Simeonov, S.D. ; Strecker, N. ; Tan, Z. ; Villablanca, L. ; Fichtner, W.</creator><creatorcontrib>Avci, I. ; Balasingam, P. ; Sayed, K.E. ; Gharib, J. ; Johnson, M.D. ; Kells, K. ; Kiralyfalvi, G. ; Koltyzhenkov, V. ; Kucherov, A. ; Lyumkis, E. ; Penzin, O. ; Polsky, B. ; Rao, V. ; Simeonov, S.D. ; Strecker, N. ; Tan, Z. ; Villablanca, L. ; Fichtner, W.</creatorcontrib><description>Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.</description><identifier>ISSN: 0749-6877</identifier><identifier>ISBN: 1424402670</identifier><identifier>ISBN: 9781424402670</identifier><identifier>EISSN: 2375-5350</identifier><identifier>EISBN: 9781424402687</identifier><identifier>EISBN: 1424402689</identifier><identifier>DOI: 10.1109/UGIM.2006.4286350</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Boron ; Etching ; Implants ; Material properties ; MOSFET circuits ; Robustness ; Shadow mapping ; Stress ; Tellurium</subject><ispartof>2006 16th Biennial University/Government/Industry Microelectronics Symposium, 2006, p.41-46</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4286350$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4286350$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Avci, I.</creatorcontrib><creatorcontrib>Balasingam, P.</creatorcontrib><creatorcontrib>Sayed, K.E.</creatorcontrib><creatorcontrib>Gharib, J.</creatorcontrib><creatorcontrib>Johnson, M.D.</creatorcontrib><creatorcontrib>Kells, K.</creatorcontrib><creatorcontrib>Kiralyfalvi, G.</creatorcontrib><creatorcontrib>Koltyzhenkov, V.</creatorcontrib><creatorcontrib>Kucherov, A.</creatorcontrib><creatorcontrib>Lyumkis, E.</creatorcontrib><creatorcontrib>Penzin, O.</creatorcontrib><creatorcontrib>Polsky, B.</creatorcontrib><creatorcontrib>Rao, V.</creatorcontrib><creatorcontrib>Simeonov, S.D.</creatorcontrib><creatorcontrib>Strecker, N.</creatorcontrib><creatorcontrib>Tan, Z.</creatorcontrib><creatorcontrib>Villablanca, L.</creatorcontrib><creatorcontrib>Fichtner, W.</creatorcontrib><title>Three-dimensional TCAD Process and Device Simulations</title><title>2006 16th Biennial University/Government/Industry Microelectronics Symposium</title><addtitle>UGIM</addtitle><description>Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.</description><subject>Annealing</subject><subject>Boron</subject><subject>Etching</subject><subject>Implants</subject><subject>Material properties</subject><subject>MOSFET circuits</subject><subject>Robustness</subject><subject>Shadow mapping</subject><subject>Stress</subject><subject>Tellurium</subject><issn>0749-6877</issn><issn>2375-5350</issn><isbn>1424402670</isbn><isbn>9781424402670</isbn><isbn>9781424402687</isbn><isbn>1424402689</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kNtKw0AYhNcTGGseQLzJC2z897x7WdJaCxUF0-uy2fzBlSaVbBV8ewPWuZmL-RiGIeSOQckYuIftav1ccgBdSm61UHBGcmcsk1xK4Nqac5JxYRRVU3ZBbv4DA5ckAyMdnRhzTfKUPmCSVFIYmxFVv4-ItI09DikeBr8v6mq-KF7HQ8CUCj-0xQK_Y8DiLfZfe3-coHRLrjq_T5iffEa2j8u6eqKbl9W6mm9oZKCOVDkvG-YbJx0L3sgGbHBacxRKGYu6mwYK3jLBrJUMtA6hbR1z3oDnwnZiRu7_eiMi7j7H2PvxZ3d6QPwClbxIdg</recordid><startdate>200606</startdate><enddate>200606</enddate><creator>Avci, I.</creator><creator>Balasingam, P.</creator><creator>Sayed, K.E.</creator><creator>Gharib, J.</creator><creator>Johnson, M.D.</creator><creator>Kells, K.</creator><creator>Kiralyfalvi, G.</creator><creator>Koltyzhenkov, V.</creator><creator>Kucherov, A.</creator><creator>Lyumkis, E.</creator><creator>Penzin, O.</creator><creator>Polsky, B.</creator><creator>Rao, V.</creator><creator>Simeonov, S.D.</creator><creator>Strecker, N.</creator><creator>Tan, Z.</creator><creator>Villablanca, L.</creator><creator>Fichtner, W.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200606</creationdate><title>Three-dimensional TCAD Process and Device Simulations</title><author>Avci, I. ; Balasingam, P. ; Sayed, K.E. ; Gharib, J. ; Johnson, M.D. ; Kells, K. ; Kiralyfalvi, G. ; Koltyzhenkov, V. ; Kucherov, A. ; Lyumkis, E. ; Penzin, O. ; Polsky, B. ; Rao, V. ; Simeonov, S.D. ; Strecker, N. ; Tan, Z. ; Villablanca, L. ; Fichtner, W.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i105t-59a4b1ab9491ca74b08c9662e35578e6f02632d1318841066ccdd919a70a238f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Annealing</topic><topic>Boron</topic><topic>Etching</topic><topic>Implants</topic><topic>Material properties</topic><topic>MOSFET circuits</topic><topic>Robustness</topic><topic>Shadow mapping</topic><topic>Stress</topic><topic>Tellurium</topic><toplevel>online_resources</toplevel><creatorcontrib>Avci, I.</creatorcontrib><creatorcontrib>Balasingam, P.</creatorcontrib><creatorcontrib>Sayed, K.E.</creatorcontrib><creatorcontrib>Gharib, J.</creatorcontrib><creatorcontrib>Johnson, M.D.</creatorcontrib><creatorcontrib>Kells, K.</creatorcontrib><creatorcontrib>Kiralyfalvi, G.</creatorcontrib><creatorcontrib>Koltyzhenkov, V.</creatorcontrib><creatorcontrib>Kucherov, A.</creatorcontrib><creatorcontrib>Lyumkis, E.</creatorcontrib><creatorcontrib>Penzin, O.</creatorcontrib><creatorcontrib>Polsky, B.</creatorcontrib><creatorcontrib>Rao, V.</creatorcontrib><creatorcontrib>Simeonov, S.D.</creatorcontrib><creatorcontrib>Strecker, N.</creatorcontrib><creatorcontrib>Tan, Z.</creatorcontrib><creatorcontrib>Villablanca, L.</creatorcontrib><creatorcontrib>Fichtner, W.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Avci, I.</au><au>Balasingam, P.</au><au>Sayed, K.E.</au><au>Gharib, J.</au><au>Johnson, M.D.</au><au>Kells, K.</au><au>Kiralyfalvi, G.</au><au>Koltyzhenkov, V.</au><au>Kucherov, A.</au><au>Lyumkis, E.</au><au>Penzin, O.</au><au>Polsky, B.</au><au>Rao, V.</au><au>Simeonov, S.D.</au><au>Strecker, N.</au><au>Tan, Z.</au><au>Villablanca, L.</au><au>Fichtner, W.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Three-dimensional TCAD Process and Device Simulations</atitle><btitle>2006 16th Biennial University/Government/Industry Microelectronics Symposium</btitle><stitle>UGIM</stitle><date>2006-06</date><risdate>2006</risdate><spage>41</spage><epage>46</epage><pages>41-46</pages><issn>0749-6877</issn><eissn>2375-5350</eissn><isbn>1424402670</isbn><isbn>9781424402670</isbn><eisbn>9781424402687</eisbn><eisbn>1424402689</eisbn><abstract>Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.</abstract><pub>IEEE</pub><doi>10.1109/UGIM.2006.4286350</doi><tpages>6</tpages></addata></record>
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2375-5350
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Annealing
Boron
Etching
Implants
Material properties
MOSFET circuits
Robustness
Shadow mapping
Stress
Tellurium
title Three-dimensional TCAD Process and Device Simulations
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T01%3A36%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Three-dimensional%20TCAD%20Process%20and%20Device%20Simulations&rft.btitle=2006%2016th%20Biennial%20University/Government/Industry%20Microelectronics%20Symposium&rft.au=Avci,%20I.&rft.date=2006-06&rft.spage=41&rft.epage=46&rft.pages=41-46&rft.issn=0749-6877&rft.eissn=2375-5350&rft.isbn=1424402670&rft.isbn_list=9781424402670&rft_id=info:doi/10.1109/UGIM.2006.4286350&rft_dat=%3Cieee_6IE%3E4286350%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424402687&rft.eisbn_list=1424402689&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4286350&rfr_iscdi=true