An Analytical Model for Reliability Evaluation of NoC Architectures
This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC...
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| creator | Dalirsani, A. Hosseinabady, M. Navabi, Z. |
| description | This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC according to their impact on system functionality. Based on this classification, the contribution of each transient fault lowering the reliability of the NoC is calculated. This model can be used to decide which fault tolerant techniques cause more improvement on system reliability. |
| doi_str_mv | 10.1109/IOLTS.2007.13 |
| format | Conference Proceeding |
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This model can be used to decide which fault tolerant techniques cause more improvement on system reliability.</description><subject>Analytical models</subject><subject>Circuit faults</subject><subject>Erbium</subject><subject>Error correction</subject><subject>Fault tolerant systems</subject><subject>Integrated circuit interconnections</subject><subject>Network-on-a-chip</subject><subject>Reliability</subject><subject>Switches</subject><subject>System-on-a-chip</subject><issn>1942-9398</issn><issn>1942-9401</issn><isbn>0769529186</isbn><isbn>9780769529189</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1zLtOwzAUgGGLi0RbGJlY_AIJ9vElPmMUlVIpUAnKXNmxI4xMghIXqW_PAEz_8Ek_IbeclZwzvN_u2v1rCYxVJRdnZMFRQoGS8XOyZJVGBciNvvgHgeaKLOf5gzGlEWFBmnqg9WDTKcfOJvo0-pBoP070JaRoXUwxn-j626ajzXEc6NjT57Gh9dS9xxy6fJzCfE0ue5vmcPPXFXl7WO-bx6LdbbZN3RYdcMyFcFZ22oJBoZSUDFAAYjDe-F4F6dBKDd4q6bwDJVzvQWgMXqpgKtdXYkXufr8xhHD4muKnnU4HCZU0wMQPNOpK0Q</recordid><startdate>200707</startdate><enddate>200707</enddate><creator>Dalirsani, A.</creator><creator>Hosseinabady, M.</creator><creator>Navabi, Z.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200707</creationdate><title>An Analytical Model for Reliability Evaluation of NoC Architectures</title><author>Dalirsani, A. ; Hosseinabady, M. ; Navabi, Z.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c219t-3ba4c6a289355440293299e8d8df5e4b9a462da54bdb253bfd2369ed45e87bf73</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Analytical models</topic><topic>Circuit faults</topic><topic>Erbium</topic><topic>Error correction</topic><topic>Fault tolerant systems</topic><topic>Integrated circuit interconnections</topic><topic>Network-on-a-chip</topic><topic>Reliability</topic><topic>Switches</topic><topic>System-on-a-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Dalirsani, A.</creatorcontrib><creatorcontrib>Hosseinabady, M.</creatorcontrib><creatorcontrib>Navabi, Z.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dalirsani, A.</au><au>Hosseinabady, M.</au><au>Navabi, Z.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An Analytical Model for Reliability Evaluation of NoC Architectures</atitle><btitle>13th IEEE International On-Line Testing Symposium (IOLTS 2007)</btitle><stitle>IOLTS</stitle><date>2007-07</date><risdate>2007</risdate><spage>49</spage><epage>56</epage><pages>49-56</pages><issn>1942-9398</issn><eissn>1942-9401</eissn><isbn>0769529186</isbn><isbn>9780769529189</isbn><abstract>This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. 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| identifier | ISSN: 1942-9398 |
| ispartof | 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007, p.49-56 |
| issn | 1942-9398 1942-9401 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models Circuit faults Erbium Error correction Fault tolerant systems Integrated circuit interconnections Network-on-a-chip Reliability Switches System-on-a-chip |
| title | An Analytical Model for Reliability Evaluation of NoC Architectures |
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