An Analytical Model for Reliability Evaluation of NoC Architectures

An Analytical Model for Reliability Evaluation of NoC Architectures

This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC...

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Hauptverfasser: Dalirsani, A., Hosseinabady, M., Navabi, Z.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Circuit faults
Erbium
Error correction
Fault tolerant systems
Integrated circuit interconnections
Network-on-a-chip
Reliability
Switches
System-on-a-chip
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Beschreibung
Zusammenfassung:This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC according to their impact on system functionality. Based on this classification, the contribution of each transient fault lowering the reliability of the NoC is calculated. This model can be used to decide which fault tolerant techniques cause more improvement on system reliability.
ISSN:1942-9398
1942-9401
DOI:10.1109/IOLTS.2007.13