A CMOS analog frontend for a passive UHF RFID tag

A CMOS analog frontend for a passive UHF RFID tag

The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC~18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock gen...

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Bibliographische Detailangaben
Hauptverfasser: Facen, Alessio, Boni, Andrea
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Antenna accessories
Bridge circuits
Charge pumps
Clocks
CMOS technology
Design
electromagnetic coupling
Hardware > Integrated circuits
IEC standards
ISO standards
Passive RFID tags
Power generation
Rectifiers
UHF integrated circuits
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Beschreibung
Zusammenfassung:The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC~18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18μm digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag.
DOI:10.1145/1165573.1165640