The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks

The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks

This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single c...

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Bibliographische Detailangaben
Hauptverfasser: Sekar, D.C., Meindl, J.D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Delay
Frequency
Logic gates
Microprocessors
Optimization methods
Parallel processing
Repeaters
Routing
Wires
Wiring
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Beschreibung
Zusammenfassung:This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels.
ISSN:2380-632X
2380-6338
DOI:10.1109/IITC.2007.382371