Power Analysis Resistant SRAM

The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 1...

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Hauptverfasser:	Konur, E., Ozelci, Y., Arikan, E., Eksi, U.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automation Charge transfer Clocks Cryptography Decoding Energy consumption Hardware Logic Power Analysis Random access memory Read-write memory Secure memories Side-Channel Analysis SRAM
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creator	Konur, E. Ozelci, Y. Arikan, E. Eksi, U.
description	The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 10 times compared to standard SRAM at the expense of higher power and silicon area consumption. Modifications on the primitive SRAM cell, address decoding logic and write operation were made to reduce the dependency.
doi_str_mv	10.1109/WAC.2006.375932
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4259848</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4259848</ieee_id><sourcerecordid>4259848</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-fbb731d769a807d7ce8871c7001816abe91dbf4228383a1c2c749ec3ba4238373</originalsourceid><addsrcrecordid>eNotjE1LxDAURR-o4DjO2oUI_QOt7-UlzcuyFL9gRBkHXA5JmkJlHKUpyPx7C3oX93DP4gJcEVZE6G7fm7ZSiHXF1jhWJ3BBIo7ZMLtTWCgyutSi9Dmscv7AOWaejAu4ef36SWPRHPz-mIdcbNLckz9Mxdumeb6Es97vc1r9cwnb-7tt-1iuXx6e2mZdDg6nsg_BMnW2dl7QdjYmEUvRIpJQ7UNy1IVeKyUs7CmqaLVLkYPXajaWl3D9dzuklHbf4_Dpx-NOK-NEC_8C1w463g</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Power Analysis Resistant SRAM</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Konur, E. ; Ozelci, Y. ; Arikan, E. ; Eksi, U.</creator><creatorcontrib>Konur, E. ; Ozelci, Y. ; Arikan, E. ; Eksi, U.</creatorcontrib><description>The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 10 times compared to standard SRAM at the expense of higher power and silicon area consumption. Modifications on the primitive SRAM cell, address decoding logic and write operation were made to reduce the dependency.</description><identifier>ISSN: 2154-4824</identifier><identifier>ISBN: 1889335339</identifier><identifier>ISBN: 9781889335339</identifier><identifier>DOI: 10.1109/WAC.2006.375932</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automation ; Charge transfer ; Clocks ; Cryptography ; Decoding ; Energy consumption ; Hardware ; Logic ; Power Analysis ; Random access memory ; Read-write memory ; Secure memories ; Side-Channel Analysis ; SRAM</subject><ispartof>2006 World Automation Congress, 2006, p.1-6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4259848$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4259848$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Konur, E.</creatorcontrib><creatorcontrib>Ozelci, Y.</creatorcontrib><creatorcontrib>Arikan, E.</creatorcontrib><creatorcontrib>Eksi, U.</creatorcontrib><title>Power Analysis Resistant SRAM</title><title>2006 World Automation Congress</title><addtitle>WAC</addtitle><description>The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 10 times compared to standard SRAM at the expense of higher power and silicon area consumption. Modifications on the primitive SRAM cell, address decoding logic and write operation were made to reduce the dependency.</description><subject>Automation</subject><subject>Charge transfer</subject><subject>Clocks</subject><subject>Cryptography</subject><subject>Decoding</subject><subject>Energy consumption</subject><subject>Hardware</subject><subject>Logic</subject><subject>Power Analysis</subject><subject>Random access memory</subject><subject>Read-write memory</subject><subject>Secure memories</subject><subject>Side-Channel Analysis</subject><subject>SRAM</subject><issn>2154-4824</issn><isbn>1889335339</isbn><isbn>9781889335339</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjE1LxDAURR-o4DjO2oUI_QOt7-UlzcuyFL9gRBkHXA5JmkJlHKUpyPx7C3oX93DP4gJcEVZE6G7fm7ZSiHXF1jhWJ3BBIo7ZMLtTWCgyutSi9Dmscv7AOWaejAu4ef36SWPRHPz-mIdcbNLckz9Mxdumeb6Es97vc1r9cwnb-7tt-1iuXx6e2mZdDg6nsg_BMnW2dl7QdjYmEUvRIpJQ7UNy1IVeKyUs7CmqaLVLkYPXajaWl3D9dzuklHbf4_Dpx-NOK-NEC_8C1w463g</recordid><startdate>200607</startdate><enddate>200607</enddate><creator>Konur, E.</creator><creator>Ozelci, Y.</creator><creator>Arikan, E.</creator><creator>Eksi, U.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200607</creationdate><title>Power Analysis Resistant SRAM</title><author>Konur, E. ; Ozelci, Y. ; Arikan, E. ; Eksi, U.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-fbb731d769a807d7ce8871c7001816abe91dbf4228383a1c2c749ec3ba4238373</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Automation</topic><topic>Charge transfer</topic><topic>Clocks</topic><topic>Cryptography</topic><topic>Decoding</topic><topic>Energy consumption</topic><topic>Hardware</topic><topic>Logic</topic><topic>Power Analysis</topic><topic>Random access memory</topic><topic>Read-write memory</topic><topic>Secure memories</topic><topic>Side-Channel Analysis</topic><topic>SRAM</topic><toplevel>online_resources</toplevel><creatorcontrib>Konur, E.</creatorcontrib><creatorcontrib>Ozelci, Y.</creatorcontrib><creatorcontrib>Arikan, E.</creatorcontrib><creatorcontrib>Eksi, U.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Konur, E.</au><au>Ozelci, Y.</au><au>Arikan, E.</au><au>Eksi, U.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power Analysis Resistant SRAM</atitle><btitle>2006 World Automation Congress</btitle><stitle>WAC</stitle><date>2006-07</date><risdate>2006</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><issn>2154-4824</issn><isbn>1889335339</isbn><isbn>9781889335339</isbn><abstract>The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 10 times compared to standard SRAM at the expense of higher power and silicon area consumption. Modifications on the primitive SRAM cell, address decoding logic and write operation were made to reduce the dependency.</abstract><pub>IEEE</pub><doi>10.1109/WAC.2006.375932</doi><tpages>6</tpages></addata></record>
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Automation Charge transfer Clocks Cryptography Decoding Energy consumption Hardware Logic Power Analysis Random access memory Read-write memory Secure memories Side-Channel Analysis SRAM
title	Power Analysis Resistant SRAM
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T19%3A54%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Power%20Analysis%20Resistant%20SRAM&rft.btitle=2006%20World%20Automation%20Congress&rft.au=Konur,%20E.&rft.date=2006-07&rft.spage=1&rft.epage=6&rft.pages=1-6&rft.issn=2154-4824&rft.isbn=1889335339&rft.isbn_list=9781889335339&rft_id=info:doi/10.1109/WAC.2006.375932&rft_dat=%3Cieee_6IE%3E4259848%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4259848&rfr_iscdi=true