A 0.18μm CMOS 2.1GHz Sub-sampling Receiver Front End with Fully Integrated Second- and Fourth-Order Q-Enhanced Filters

The implementation of a 0.18μm CMOS 2.1GHz sub-sampling receiver front end with fully integrated fourth- and second- order Q-enhanced LC filters is described. The use of an integrated fourth- order filter allows the amount of noise aliasing due to sub-sampling to be reduced and the bandwidth and roll-off factor to be independently controlled. When tuned to a high effective quality factor of 210, the front end has a measured bandwidth of 14MHz, a passband flatness of +/-0.4dB, a gain of 34dB and an input IP3 of 31.7dBm. The simulated noise figure of the front end is 7.12dB, which is lower than that of previously published sub-sampling front ends using off-chip inductors. The total power consumption of the front end is 28.5mA from a 1.8V supply.