An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable Multiprocessor

A reconfigurable Viterbi decoder capable of accommodating K from 6 to 9, and r = 1/2 and 1/3 has been implemented on a programmable multiprocessor, fabricated in TSMC 0.18- μ m CMOS. Efficient trellis partitioning and path metric memory localization techniques endow the Viterbi decoder with simple configuration control and high efficiency. For this Viterbi decoder, performance can be traded off in favor of power savings, or vice-versa.