A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of

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Bibliographische Detailangaben
Hauptverfasser:	Harwood, Mike, Warke, Nirmal, Simpson, Richard, Leslie, Tom, Amerasekera, Ajith, Batty, Sean, Colman, Derek, Carr, Eugenia, Gopinathan, Venu, Hubbins, Steve, Hunt, Peter, Joy, Andy, Khandelwal, Pulkit, Killips, Bob, Krause, Thomas, Lytollis, Shaun, Pickering, Andy, Saxton, Mark, Sebastio, David, Swanson, Graeme, Szczepanek, Andre, Ward, Terry, Williams, Jeff, Williams, Richard, Willwerth, Tom
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Backplanes Clocks Decision feedback equalizers Delay Error-free operation Finite impulse response filter Intersymbol interference Jitter Phase locked loops Timing
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Beschreibung
Zusammenfassung:	A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of
ISSN:	0193-6530 2376-8606
DOI:	10.1109/ISSCC.2007.373481