A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided V DD line is adopted in the memory array to assist the write. Two SRAM cells with a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Yabuuchi, Makoto, Nii, Koji, Tsukamoto, Yasumasa, Ohbayashi, Shigeki, Imaoka, Susumu, Makino, Hiroshi, Yamagami, Yoshinobu, Ishikura, Satoshi, Terano, Toshio, Oashi, Toshiyuki, Hashimoto, Keiji, Sebe, Akio, Okazaki, Gen, Satomi, Katsuji, Akamatsu, Hironori, Shinohara, Hirofumi
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit simulation
CMOS technology
Decoding
Degradation
Driver circuits
MOS devices
Random access memory
Rats
Temperature dependence
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided V DD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum 2 and 0.327mum 2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2007.373426