A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS

A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS

Time-domain randomization of the unit current-cell refresh period converts the tonal behavior of cyclic background calibration into noise. Together with nested calibration of all DAC-segments a low-frequency SFDR of 83.7dB is achieved. The chip is fabricated in a standard 0.13mum CMOS process. Clock...

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Bibliographische Detailangaben
Hauptverfasser: Clara, Martin, Klatzer, Wolfgang, Seger, Berthold, di Giandomenico, Antonio, Gori, Luca
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Calibration
Clocks
CMOS technology
Energy consumption
Frequency
Noise shaping
Solid state circuits
Time domain analysis
Voltage
Wideband
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Beschreibung
Zusammenfassung:Time-domain randomization of the unit current-cell refresh period converts the tonal behavior of cyclic background calibration into noise. Together with nested calibration of all DAC-segments a low-frequency SFDR of 83.7dB is achieved. The chip is fabricated in a standard 0.13mum CMOS process. Clocked at 200MHz, it consumes 25mW from a 1.5V supply.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2007.373388