A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2ps rms jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum 2 in a 0.13mum CMOS process and dis...

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Bibliographische Detailangaben
Hauptverfasser: Oh, Do-Hwan, Kim, Deok-Soo, Kim, Suhwan, Jeong, Deog-Kyoon, Kim, Wonchan
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Circuit optimization
Clocks
Frequency
IIR filters
Jitter
Logic
Routing
Switches
Tuning
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Beschreibung
Zusammenfassung:A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2ps rms jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum 2 in a 0.13mum CMOS process and dissipates 13.2mW from a 1.2V supply when operating at 2.5Gb/s.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2007.373374