A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm 2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance u...

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Hauptverfasser: Chen, Zongjian, Ananthanarayanan, Priya, Biswas, Sukalpa, Campbell, Brian, Chen, Hao, Desai, Shailendra, Desai, Shaishav, Go, Dominic, Goel, Rajat, von Kaenel, Vincent, Kassoff, Jason, Klass, Fabian, Ku, Weichun, Li, Tony, Lin, Jonathon, Malik, Khurram, Mehta, Anup, Murray, Dan, Shiu, Eric, Shuler, Chris, Santhanam, Sribalan, Scott, Greg, Sugisawa, Junji, Takayanagi, Toshinari, Tam, Honkai John, Trivedi, Pradeep, Wang, James, Wen, Ricky, Yong, John
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Delay
Frequency
Phase detection
Random access memory
Table lookup
Temperature
Voltage
Writing
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Beschreibung
Zusammenfassung:An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm 2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2007.373609